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Mask Design Engineer Company Name: Linear Technology Corporation Responsible for the layout schedule estimation, IC layout floor planning, Layout of analog and digital circuits, Cell level verification and parasitic extraction, Chip/Top level routing and interconnect, LVS and DRC checks using Cadence Dracula and Assura; Tape out/Stream out/PG. Minimum job requirements: Bachelors degree in Electrical Engineering, Microelectronics Engineering or related field and at least five year experience in IC layout. Must have. After registering you may be able to apply for this job directly (if still active) on ((None))'s site. Future job matches may be sent from Geebo approved job partners.
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